This invention relates to an apparatus and method for testing an open or conductivity of circuit pathways formed on a substrate. the substrate may be a printed circuit board, a glass plate carrying transparent conductors for a liquid crystal display and plasma display panel, a semiconductor package, film carrier, and the like. The circuit pathways are electric conductors as may be identified as lines, traces, tracks, or wiring through which electric signals are transmitted or conveyed.
After a circuit board is formed with electric circuit pathways, conductivity of a pathway and leakage of a current from a pathway to the other are generally tested or inspected for the substrate by means of a circuit board testing apparatus. Such test, sometimes referred to as bare board test, is carried out before electronic devices are mounted on the circuit board in order to determine whether or not the circuit pathways have been properly formed.
One circuit board testing apparatus and method are disclosed in U.S. Pat. No. 5,969,530 co-assigned to the same assignee as that of the present application. The disclosure of the U.S. Patent is incorporated herein by reference. According to this testing method, conductivity test is made with a probe being in contact with one end of a circuit pathway, while an electrode being opposed to the other end of the circuit pathway with a gap to form a capacitive coupling. According to that testing method, a test signal of which electric parameter changes, is supplied to the probe, runs through the pathway and is picked up through the capacitive coupling. The signal may be sinusoidal or sine wave signal, a pulse signal, or a signal appearing when a switch is turned on or off to connect or disconnect a direct current to the probe. Thus, the signal changes its electric parameter to pass through the capacitive coupling between the electrode and the wiring. The prior art method is advantageous in that the electrode may cover a plurality of circuit pathways and that conductivity is tested even if the pitches between the adjacent pathways are small.
However, the testing apparatus and method according to the embodiments as disclosed in the above-mentioned U.S. Pat. No. 5,969,530 have difficulty in detecting when the circuit pathway extends on both surfaces of the board and wirings of the pathway on the both surfaces of the board oppose to each other. The following description with reference to FIGS. 14A and 14B will clarify the difficulty.
With reference to FIGS. 14A and 14B, a wiring 101 formed on a bottom surface of a printed circuit board 100 under test and a wiring 102 formed on a top surface of the board 100 are electrically connected through a viahole conductor 103 with the wirings 101 and 102 opposing to each other. The conductivity of the pathway comprised of the wirings 101 and 102 is detected based on an output derived from a planar electrode 105 located above the wiring 102 when the circuit pathway is applied with an electric signal through the probe 104. It is expected that the electric signal picked up by the electrode 105 is zero or low when an interruption exists on the pathway, while the electric signal is above a predetermined level when the pathway is continuous.
However, in the case of pathway arrangement shown in FIGS. 14A and 14B, the upper and lower wirings 101 and 102 are capacitively coupled with each other when an interruption exists 106 on the pathway. Let's assume that the capacitance for the coupling of the electrode 105 and the wiring 102 is C.sub.1, while the capacitance for the coupling of the wiring 101 and 102 is C.sub.2.
This situation is likely to occur when a plurality of wirings or electrically conductive layers are formed on one surface of a circuit board or substrate, with the wirings or layers vertically overlap each other or located one above another.
Also, this situation will occur not only with circuit boards but also with other substrates such as a glass or other transparent substrate for a liquid crystal display and a plasma display, a semiconductor package, and film carrier.
In the case that there is the interruption 106 in the wiring 102 as shown in FIGS. 14A and 14B, a total of capacitances Ct between the lower wiring 101 and the planar electrode 105 will be EQU C.sub.t =C.sub.1 C.sub.2 /(C.sub.1 +C.sub.2) (1).
In the case that the circuit pathway is continuous, i.e., electrically connected, the total capacitance is equal to the single capacitance C.sub.1 since the oppositely arranged wirings 101 and 102 are connected with each other and the capacitance C.sub.2 does not appear, that is, the opposite ends of the capacitance C.sub.2 are short-circuited.
In general, a capacitance C is expressed by EQU C=.epsilon..multidot.S/d (2)
wherein S, d and .epsilon. respectively denote an opposing area of oppositely arranged conductors, a distance between the conductors, and a permittivity of a medium between the conductors. Accordingly, the capacitances C.sub.1 and C.sub.2 are determined by the area S and the distance d if the permittivity .epsilon. of the medium constituting the board 100 is substantially the same as that of the air between the board 100 and the planar electrode 105.
In FIGS. 14A and 14B, it is assumed as the case of normal situation that the distance d.sub.1 between the planar electrode 105 and the wiring 102 is smaller than a thickness d.sub.2 of the circuit board 100, and an area S.sub.1 of the portions of the planar electrode 105 and the wiring 102 that oppose or face each other is smaller than an area S.sub.2 of the portions of the wirings 101 and 102 that oppose each other. The relationship of the capacitances C.sub.1 and C.sub.2 can be expressed: EQU C.sub.2 &gt;C.sub.1 (3)
when a ratio S.sub.2 /S.sub.1 is greater than a ratio d.sub.2 /d.sub.1. This situation normally occur when the wirings 101 and 102 oppose or face each other for a substantial extension.
Here, C.sub.2 will become very greater than C.sub.1 when the ratio S.sub.2 /S.sub.1 is considerably large. In this case, Equation (1) is rewritten as follows: ##EQU1##
Accordingly, it can be understood that the output of the planar electrode 105 is not noticeably different between in a state where the circuit pathway under test has an interruption and in a state where the circuit pathway under test has no interruption. Consequently, the conventional circuit board testing apparatus cannot satisfactorily distinguish defective circuit boards from good circuit boards in the case as discussed above.